In the operation of electronic circuits of the kind that employ a clock to synchronize successive steps of the circuits' operation, it is desirable to keep the clock period as short as possible (timing optimization) to increase the number of clock cycles that can be carried out in a given time, thereby either to decrease the time to accomplish a given operation or to increase the amount of information that can be generated in a given time.
An important class of such clocked circuits are synchronous logic circuits that are formed by an interconnection of combinational logic gates and clocked flip-flops, generally described as latches. Such circuits, particularly of the VLSI size, currently are designed by computer tools. Such design is typically done by logic synthesis with little concern for timing optimization, concern for which is generally reserved for a later separate redesign stage. Various approaches have been proposed for such retiming stage. Generally, the typical approach involves an iteration of small retiming changes in the design, each followed by a testing step, that can involve many trials before the optimum is reached. Such a retiming process is time consuming.
The making of a series of small incremental changes generally is necessitated by lack of information as to what is the optimal timing that can in practice be realized in the specific circuit under design.